Some notes on sysgen FFT

The FFT is an efficient implementation of a linear transformation, it takes an N-point vector of complex data and returns an N-point vector of complex data. In Matlab it is as simple as
y = fft(x);

In sysgen we have to worry about certain other inputs (and outputs) as shown in Fig. 1 below.

Fig. 1: Xilinx Sysgen FFT block showing the various inputs and outputs

I will go over some (not all) relevant inputs, their types and how they are used:

• The input data xn_re and xn_im can be a signed data type S.(S-1), from 8 to 34 bits wide inclusive. 
• The start signal must be driven by a Bool, pulsed or set high at the start of a frame. 
• Bool fwd_inv = 0 if inverse transform, 1 if forward transform.
• Bool fwd_inv_we when asserted high loads the transform type from fwd_inv for the next input frame
• scale_sch: scaling schedule (more on this later)
• Bool scale_sch_we: when asserted high loads the scale_sch for the next input frame

Lets now discuss the non-obvious outputs

• Bool rfd active high after start signal is asserted and till xk_index (output index) reaches N-1.
• Bool busy active high when block is processing data
• Bool dv : data valid signal for output
• Bool edone, done: active high one sample period before and when frame processing and ready for output respectively.

If we double click on the block, we get a bunch of configuration options. On the Basic tab, I choose Transform Length of 1024, pipelined_streaming_io (all other settings are defaults). Under Advanced tab, we choosed Scaled, Convergent Rounding, Natural Order and check the overflow ovflo pin. 

a terse vhdl tutorial

A digital system is composed of a top-level entity which can contain other entities. Each entity (component) is modeled by an entity declaration and an architecture. The entity declaration defines the input and output ports to the entity and the architecture describes the processing involved in that entity.

1) Entity declaration has the general form (keywords in bold, things inside [ ] are optional)

entity ENTITY_NAME is

[generic ( param1 : integer := 16#00#;

param2 : integer := 16#00#

);]

port (signal1,signal2: in std_logic;

signal3: out std_ulogic;

signal4,signal5: buffer boolean;

signal6: inout std_logic_vector (7 downto 0)

);

end [ENTITY_NAME];

Generic declarations determine local constants used inside the entity. Each port needs to have a type. std_logic can take values 0,1, X (unknown value) and 6 other special values.

2) Architecture definition: defines how the circuit operates and its implementation. Some examples

a) Behavioral description

entity XNOR2 is

port in1, in2: in std_logic;

port out1: in std_logic);

end XNOR2;

architecture behavioral_xnor2 of XNOR2 is

-- This is a comment and so is the next line

-- signal declaration (of internal signals X, Y). The signal assignment is a concurrent assisgment as opposed to sequential.

signal X,Y: std_logic;

begin

X <= in1 and in2;

Y <= (not in1) and (not in2);

Z <= X or Y;

end behavioral_xnor2;

architecture structural of XNOR2 is

-- Component declarations

component AND2

port (in1, in2: in std_logic; out1: out std_logic);

end component;

component NOT1

port (in1: in std_logic;

out1: out std_logic);

end component;

component OR2

port (in1, in2: in std_logic; out1: out std_logic);

end component;`

-- signals that connect the gates

signal A,B, X,Y,Y1,Y2,Z: std_logic;

begin

-- Instantiate components and connect them

U0: AND2 port map (in1=>A,in2=>B,out1=>X);

U1: NOT1 port map (in1=>A,out1=>Y1);

U2: NOT1 port map (in1=>B,out1=>Y2);

U3: AND2 port map (in1=>Y1,in2=>Y2,out1=>Y);

U4: OR2 port map (in1=>X,in2=>Y,out1=>Z);

end structural;

Note that the order of statements above is not relevant since everything is concurrent and executed in parallel. The components declared above need to have an architecture description of their own. These can be stored in packages that can be included at the beginning of the VHDL file (similar to C header files). For example,

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

Sequential statements can be modeled using the process construct. The statements inside a process are executed sequentially. Lets look at a rising edge triggered D flip-flop

entity DFF is

port (CLK, D: in std_logic;

Q: out std_logic);

end DFF

architecture behavior_DFF of DFF is

begin

DFF_PROCESS: process (CLK)

begin

if (CLK'event and CLK = '1') then

Q <= D;

end if;

end process;

end behavior_DFF;

There are several other elements of VHDL like case statements, loops, next and exit, wait, that one may want to use. But thats it for this tutorial.

Introduction to Xilinx's sysgen

Sysgen is a simulink based tool from Xilinx that allows the matlab/simulink to FPGA design flow. I am using Xilinx ISE Design Suite 13.1 with the ML-605 (avnet) board with hosts the Virtex6 FPGA. The board connects to my laptop via tow possible ways: JTAG/usb and Ethernet.

When making a simulink block diagram that needs to be mapped to FPGA one has to use only Xilinx blocks. In particular, Xilinx "Gateway In" and "Gateway Out" blocks are used to demarcate the boundaries of what gets mapped to FPGA and what does not. "Gateway In" converts double precision input to fixed point. "Gateway Out" converts fixed to double. Also the System Generator Token is something that should be in every design. It can be configured to set target device, clock performance and some other stuff.

There is a special block called MCode block which allows one to write control logic (no vector/math operations) using the matlab language. A state variable needs to be declared (See documentation).

I will try to cover some more detailed design examples next time.

Purposes of a book

There are various needs that a book may try to fulfill, for example:

1. It may be as a textbook that students taking a class can closely follow, with several examples and homework problems, code samples, sample projects

2. It may be as a overview of the state of the art in a particular area of active research, enabling researchers a nice tutorial overview so that they can focus on thinking about unsolved problems and their solutions

3. It may be for practicing engineers who want to learn quickly how to implement a certain algorithm

4. It may be for people trying to learn about a subject for the first time but with a specific application in mind

==

Some other goals a book might have

1. Provide a unique perspective/spin on a topic with an overarching theme

2. provide several interesting ideas that are put to test under practical/real-life settings

3. reference for problem solving techniques in this area

4. some pointers/tips on useful open source tools like ns2, python (how to guides)