Introduction to Xilinx's sysgen

Sysgen is a simulink based tool from Xilinx that allows the matlab/simulink to FPGA design flow. I am using Xilinx ISE Design Suite 13.1 with the ML-605 (avnet) board with hosts the Virtex6 FPGA. The board connects to my laptop via tow possible ways: JTAG/usb and Ethernet.

When making a simulink block diagram that needs to be mapped to FPGA one has to use only Xilinx blocks. In particular, Xilinx "Gateway In" and "Gateway Out" blocks are used to demarcate the boundaries of what gets mapped to FPGA and what does not. "Gateway In" converts double precision input to fixed point. "Gateway Out" converts fixed to double. Also the System Generator Token is something that should be in every design. It can be configured to set target device, clock performance and some other stuff.

There is a special block called MCode block which allows one to write control logic (no vector/math operations) using the matlab language. A state variable needs to be declared (See documentation).

I will try to cover some more detailed design examples next time.