a terse vhdl tutorial

A digital system is composed of a top-level entity which can contain other entities. Each entity (component) is modeled by an entity declaration and an architecture. The entity declaration defines the input and output ports to the entity and the architecture describes the processing involved in that entity.

1) Entity declaration has the general form (keywords in bold, things inside [ ] are optional)

entity ENTITY_NAME is

[generic ( param1 : integer := 16#00#;

param2 : integer := 16#00#

);]

port (signal1,signal2: in std_logic;

signal3: out std_ulogic;

signal4,signal5: buffer boolean;

signal6: inout std_logic_vector (7 downto 0)

);

end [ENTITY_NAME];

Generic declarations determine local constants used inside the entity. Each port needs to have a type. std_logic can take values 0,1, X (unknown value) and 6 other special values.

2) Architecture definition: defines how the circuit operates and its implementation. Some examples

a) Behavioral description

entity XNOR2 is

port in1, in2: in std_logic;

port out1: in std_logic);

end XNOR2;

architecture behavioral_xnor2 of XNOR2 is

-- This is a comment and so is the next line

-- signal declaration (of internal signals X, Y). The signal assignment is a concurrent assisgment as opposed to sequential.

signal X,Y: std_logic;

begin

X <= in1 and in2;

Y <= (not in1) and (not in2);

Z <= X or Y;

end behavioral_xnor2;

architecture structural of XNOR2 is

-- Component declarations

component AND2

port (in1, in2: in std_logic; out1: out std_logic);

end component;

component NOT1

port (in1: in std_logic;

out1: out std_logic);

end component;

component OR2

port (in1, in2: in std_logic; out1: out std_logic);

end component;`

-- signals that connect the gates

signal A,B, X,Y,Y1,Y2,Z: std_logic;

begin

-- Instantiate components and connect them

U0: AND2 port map (in1=>A,in2=>B,out1=>X);

U1: NOT1 port map (in1=>A,out1=>Y1);

U2: NOT1 port map (in1=>B,out1=>Y2);

U3: AND2 port map (in1=>Y1,in2=>Y2,out1=>Y);

U4: OR2 port map (in1=>X,in2=>Y,out1=>Z);

end structural;

Note that the order of statements above is not relevant since everything is concurrent and executed in parallel. The components declared above need to have an architecture description of their own. These can be stored in packages that can be included at the beginning of the VHDL file (similar to C header files). For example,

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

Sequential statements can be modeled using the process construct. The statements inside a process are executed sequentially. Lets look at a rising edge triggered D flip-flop

entity DFF is

port (CLK, D: in std_logic;

Q: out std_logic);

end DFF

architecture behavior_DFF of DFF is

begin

DFF_PROCESS: process (CLK)

begin

if (CLK'event and CLK = '1') then

Q <= D;

end if;

end process;

end behavior_DFF;

There are several other elements of VHDL like case statements, loops, next and exit, wait, that one may want to use. But thats it for this tutorial.